/******************************************************************************

    File Name: configReg.h

    Include file to set the Configuration Bits of a PIC 18F452 in code.

    Vers:  1.1
    Date:  31-Oct-2010
    Name:  David Rye

    If the macro __DEBUG is defined by selecting the 'Debug' drop-down in MPLAB, 
    the configuration bits are set as appropriate for development and debugging:
        - HS Oscillator; Oscillator Switch disabled; Power-On Timer;
        - Brown-out Reset disabled;
        - Watchdog Timer disabled;
        - CCP2 Multiplex disabled;
        - Stack Overflow Reset disabled;
        - Low-voltage Programming disabled, Debug mode enabled;
        - No protection bits set.

    If the macro __DEBUG is NOT defined by selecting 'Release' in MPLAB, 
    the configuration bits are set as appropriate for production code release:
        - HS Oscillator; Oscillator Switch disabled; Power-On Timer;
        - Brown-out Reset enabled at 4.2V;
        - Watchdog Timer disabled;
        - CCP2 Multiplex disabled;
        - Stack Overflow Reset;
        - Low-voltage Programming and Debug mode disabled;
        - No protection bits set.

    Note: IMPORTANT! The configuration bits are "read" only when the processor
    starts up. If any of the configuration bits are changed the processor MUST
    BE POWER CYCLED for the change(s) to take effect.  
    
    Note: Ensure that MPLAB is configured so that the configuration bits are 
    set in code. To do this, Configure -> Configuration Bits -> tick the box. 

    Note: This file was generated by the compiler from the command line:
          mcc18 -p18f452 --help-config > configReg.h

    Bugs:  --

    ToDo:  --

    Revision History
       Vers    Date         Who?       Revision Detail?
       1.1     31-Oct-2010  DCR        Added notes on clock configuration
       1.0     12-Apr-2005  DCR        Released

******************************************************************************/


#ifndef CONFIG_REG_H
#define CONFIG_REG_H

#include <p18cxxx.h>


// Configuration settings available for 18F452 Processor
// =====================================================

#ifndef __18F452        // defined in IDE by Configure > Select Device
#error  "ERROR: Configuration-header file mismatch.  Verify selected processor."
#endif


//  Oscillator Selection:
//    OSC = LP          Low power crystal
//    OSC = XT          Crystal/resonator
//    OSC = HS          High speed crystal/resonator
//    OSC = HSPLL       HS with PLL enabled: Clock frequency = (4 x Fosc)
//    OSC = RC          RC oscillator with OSC2 pin configured as Fosc/4 output
//    OSC = RCIO        RC oscillator with OSC2 pin configured as RA6
//    OSC = EC          External clock with OSC2 pin configured as Fosc/4 output
//    OSC = ECIO        External clock with OSC2 pin configured as RA6
//
//  Oscillator Switch Enable:
//    OSCS = ON         Enabled
//    OSCS = OFF        Disabled
//
//  Power Up Timer:
//    PWRT = ON         Enabled
//    PWRT = OFF        Disabled

// Use OSC = EC    for the PICDem2 board to give Fosc =  4 MHz, Tcy = 1 usec
// Use OSC = HS    for the minimal board to give Fosc = 10 MHz, Tcy = 400 nsec
// Use OSC = HSPLL for the minimal board to give Fosc = 40 MHz, Tcy = 100 nsec
#pragma config OSC  = EC, OSCS = OFF, PWRT = ON           


//  Brown Out Reset:
//    BOR = OFF         Disabled
//    BOR = ON          Enabled
//
//  Brown Out Voltage:
//    BORV = 45         4.5V
//    BORV = 42         4.2V
//    BORV = 27         2.7V
//    BORV = 25         2.5V

#pragma config BORV = 42

#if defined (__DEBUG)           // defined by the 'Debug' drop-down in MPLAB
#pragma config BOR = OFF
#else
#pragma config BOR = ON
#endif


//  Watchdog Timer:
//    WDT = OFF         Disabled
//    WDT = ON          Enabled
//
//  Watchdog Postscaler:
//    WDTPS = 1         1:1
//    WDTPS = 2         1:2
//    WDTPS = 4         1:4
//    WDTPS = 8         1:8
//    WDTPS = 16        1:16
//    WDTPS = 32        1:32
//    WDTPS = 64        1:64
//    WDTPS = 128       1:128

#pragma config WDT = OFF, WDTPS = 128


//  CCP2 Mux:
//    CCP2MUX = OFF     Disable (CCP2 is on RB3)
//    CCP2MUX = ON      Enable  (CCP2 is on RC1)

#pragma config CCP2MUX = OFF


//  Stack Overflow Reset:
//    STVR = OFF        Disabled
//    STVR = ON         Enabled
//
//  Low Voltage ICSP:
//    LVP = OFF         Disabled
//    LVP = ON          Enabled
//
//  Background Debugger Enable:
//    DEBUG = ON        Enabled
//    DEBUG = OFF       Disabled

//  NOTE: LVP = ON is not compatible with DEBUG = ON

#if defined (__DEBUG)           // defined by the 'Debug' drop-down in MPLAB
#pragma config STVR = OFF, LVP = OFF, DEBUG = ON
#else
#pragma config STVR = ON,  LVP = OFF, DEBUG = OFF
#endif


//  Code Protection Block 0:
//    CP0 = ON          Enabled
//    CP0 = OFF         Disabled
//
//  Code Protection Block 1:
//    CP1 = ON          Enabled
//    CP1 = OFF         Disabled
//
//  Code Protection Block 2:
//    CP2 = ON          Enabled
//    CP2 = OFF         Disabled
//
//  Code Protection Block 3:
//    CP3 = ON          Enabled
//    CP3 = OFF         Disabled

#pragma config CP0 = OFF, CP1 = OFF, CP2 = OFF, CP3 = OFF


//  Boot Block Code Protection:
//    CPB = ON          Enabled
//    CPB = OFF         Disabled
//
//  Data EEPROM Code Protection:
//    CPD = ON          Enabled
//    CPD = OFF         Disabled

#pragma config CPB = OFF, CPD = OFF


//  Write Protection Block 0:
//    WRT0 = ON         Enabled
//    WRT0 = OFF        Disabled
//
//  Write Protection Block 1:
//    WRT1 = ON         Enabled
//    WRT1 = OFF        Disabled
//
//  Write Protection Block 2:
//    WRT2 = ON         Enabled
//    WRT2 = OFF        Disabled
//
//  Write Protection Block 3:
//    WRT3 = ON         Enabled
//    WRT3 = OFF        Disabled

#pragma config WRT0 = OFF, WRT1 = OFF, WRT2 = OFF, WRT3 = OFF


//  Boot Block Write Protection:
//    WRTB = ON         Enabled
//    WRTB = OFF        Disabled
//
//  Configuration Register Write Protection:
//    WRTC = ON         Enabled
//    WRTC = OFF        Disabled
//
//  Data EEPROM Write Protection:
//    WRTD = ON         Enabled
//    WRTD = OFF        Disabled

#pragma config WRTB = OFF, WRTC = OFF, WRTD = OFF


//  Table Read Protection Block 0:
//    EBTR0 = ON        Enabled
//    EBTR0 = OFF       Disabled
//
//  Table Read Protection Block 1:
//    EBTR1 = ON        Enabled
//    EBTR1 = OFF       Disabled
//
//  Table Read Protection Block 2:
//    EBTR2 = ON        Enabled
//    EBTR2 = OFF       Disabled
//
//  Table Read Protection Block 3:
//    EBTR3 = ON        Enabled
//    EBTR3 = OFF       Disabled

#pragma config EBTR0 = OFF, EBTR1 = OFF, EBTR2 = OFF, EBTR3 = OFF


//  Boot Block Table Read Protection:
//    EBTRB = ON        Enabled
//    EBTRB = OFF       Disabled

#pragma config EBTRB = OFF


#endif  // #ifndef CONFIG_REG_H

